Project 04 / Building a tool

Can an ASIC flow
explain every result?

I’m building TapeItOut to make open-source ASIC flows easier to run and compare, with reports that show how each run went.

Yosys · LibreLane · OpenROAD · OpenSTA ● Building Flow Engine

Start with a run you can reproduce.

I’m automating runs through open-source ASIC tools, from synthesis and floorplanning to routing and static timing analysis (STA). The aim is to make regression checks and quality-of-results reports easier to repeat and compare.

What every run should tell you: What passed, what failed, what remains unclear, and which logs back up the result.

Where I’d like to take it

TapeItOut’s broader vision is an accessible, reproducible environment for chip design: start with clear constraints, simulate, revise, inspect DRC/LVS violations visually, and gradually move toward FPGA prototyping and ASIC tapeouts.

Where things stand

TapeItOut isn’t a finished product yet. Right now I’m focused on making the flow automation and reports repeatable before adding more.

Next steps

I want to make runs repeatable across Linux setups, make timing and congestion maps easier to read, and test the workflow with student designers before expanding it.

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