Project 06 / Architecture exploration

Exploring hardware
for post-quantum cryptography.

I’m exploring a programmable hardware platform for post-quantum cryptography, with TSMC 28 nm as the target process.

PQC · APB4 · AXI4 ● Architecture work · Not fabricated

What should the fabric accelerate?

The idea is to share hardware across post-quantum cryptography algorithms while keeping data movement fast and memory boundaries secure. This is still at the architecture stage, so the blocks below are planned features, not implemented results.

Architecture scope

Shared NTT/INTT engine and modular polynomial arithmetic.
Keccak-f[1600] state hashing support.
Dedicated X25519 elliptic curve datapath.
ML-KEM-512/768/1024 and ML-DSA-44/65/87 algorithm targets.

Interfaces and security

APB4 control register interface, AXI4 master/slave data movement, secure scratchpad memory, internal key vault, TRNG/DRBG, and a security root-of-trust controller form the architectural roadmap.

Target: TSMC 28 nm. This design has not been fabricated, so there are no silicon measurements.

What needs to happen before implementation

Before building it, I need to settle which algorithm parameter sets to support, define the threat model, and estimate the scheduling and memory traffic. Then I can verify correctness and constant-time behavior before moving on to physical design.

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