TSMC 65 nm GP · Architecture Target
● Architectural Specification
How do four converters behave as one?
The idea is to use four converters together in a PAM4 SerDes receiver. They need to keep up with the data while controlling timing skew, offset, and gain mismatch between channels.
How it’s designed
Each channel uses an 8-bit nonbinary SAR conversion with loop-unrolled 2-bit-per-cycle decisions. Four channels are time-interleaved and followed by a 4:1 mux/deskew path. Background calibration is planned for offset, gain, sampling skew and comparator mismatch.
Still a target: 4 channels × 500 MS/s each = 2.0 GS/s aggregate throughput. This is an architectural goal, not a measured result.
Other goals
- 5–6 conversion cycles per channel.
- Less than 1.0 ps RMS inter-channel sampling skew.
- 33.4 mW typical and 41.2 mW maximum total power targets.
What I need to prove
I still need to check the nonbinary search margins, test whether calibration settles reliably, and work out the circuit’s power and noise budget. Until then, these numbers are goals, not implementation results.
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