Bring sensing and inference closer.
We’re bringing a small RISC-V core, neural-network accelerators, and data movement together for edge anomaly detection. The project is in development with the Chip Designers Guild at VIT Chennai.
What we’re building
- Ibex RV32IM CPU core.
- INT8 neural processing unit with 64 MACs.
- 256-neuron LIF spiking neural network accelerator.
- Four-channel DMA and Wishbone interconnect.
SCL180 is the target process. The architecture and implementation are still in development; there has been no tapeout or silicon measurement.
My part in it
As the Guild’s founder and captain, I help coordinate the RTL, verification, FPGA prototype, and ASIC flow. We’re also learning the less visible parts of integration: interfaces, memory movement, reset behavior, and tests we can repeat.
What I’ll share next
Next, I plan to share a repeatable regression summary, an FPGA demo, and an implementation report. I’ll include the RTL revision, tool versions, constraints, and PDK assumptions so the results can be checked.
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